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<div class="header">
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<a href="#nested-classes">Data Structures</a> &#124;
<a href="#enum-members">Enumerations</a>  </div>
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<div class="title">Data Structures<div class="ingroups"><a class="el" href="group__group__sysclk.html">SysClk       (System Clock)</a> &raquo; <a class="el" href="group__group__sysclk__pll.html">Phase Locked Loop (PLL)</a></div></div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pll__config__t.html">cy_stc_pll_config_t</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure containing information for configuration of a PLL.  <a href="structcy__stc__pll__config__t.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html">cy_stc_dpll_lp_config_t</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure containing information for configuration of a DPLL-LP.  <a href="structcy__stc__dpll__lp__config__t.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html">cy_stc_dpll_hp_config_t</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure containing information for configuration of a DPLL-HP.  <a href="structcy__stc__dpll__hp__config__t.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pll__manual__config__t.html">cy_stc_pll_manual_config_t</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure containing information for manual configuration of a PLL.  <a href="structcy__stc__pll__manual__config__t.html#details">More...</a><br /></td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a>
Enumerations</h2></td></tr>
<tr class="memitem:gaf99eec425e4a077026c29fca5f2e7f47"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__pll__structs.html#gaf99eec425e4a077026c29fca5f2e7f47">cy_en_wait_mode_select_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__sysclk__pll__structs.html#ggaf99eec425e4a077026c29fca5f2e7f47a030904943a55de752048728289437ae3">CY_SYSCLK_DPLL_HP_CLK4MHZ_1US_CNT_VAL</a> = 0U, 
<br />
&#160;&#160;<a class="el" href="group__group__sysclk__pll__structs.html#ggaf99eec425e4a077026c29fca5f2e7f47ac907d199f7ebde8e2ebe0f0f71e6cea0">CY_SYSCLK_DPLL_HP_CLK10MHZ_1US_CNT_VAL</a> = 1U, 
<br />
&#160;&#160;<a class="el" href="group__group__sysclk__pll__structs.html#ggaf99eec425e4a077026c29fca5f2e7f47a3581bc4d3e968bba9f91209a583b7261">CY_SYSCLK_DPLL_HP_CLK15MHZ_1US_CNT_VAL</a> = 2U, 
<br />
&#160;&#160;<a class="el" href="group__group__sysclk__pll__structs.html#ggaf99eec425e4a077026c29fca5f2e7f47ae3a306e2ba52c1aed04d1fbd977c1eae">CY_SYSCLK_DPLL_HP_CLK20MHZ_1US_CNT_VAL</a> = 3U, 
<br />
&#160;&#160;<a class="el" href="group__group__sysclk__pll__structs.html#ggaf99eec425e4a077026c29fca5f2e7f47ac3972a0491f06b1efa46cbe78178cb2e">CY_SYSCLK_DPLL_HP_CLK30MHZ_1US_CNT_VAL</a> = 4U, 
<br />
&#160;&#160;<a class="el" href="group__group__sysclk__pll__structs.html#ggaf99eec425e4a077026c29fca5f2e7f47a7235d2e5aaa2b4db0c0e8c9ee7ebc818">CY_SYSCLK_DPLL_HP_CLK40MHZ_1US_CNT_VAL</a> = 5U, 
<br />
&#160;&#160;<a class="el" href="group__group__sysclk__pll__structs.html#ggaf99eec425e4a077026c29fca5f2e7f47ac81cadd73490b1cb782c2a41ec422d9d">CY_SYSCLK_DPLL_HP_CLK45MHZ_1US_CNT_VAL</a> = 6U, 
<br />
&#160;&#160;<a class="el" href="group__group__sysclk__pll__structs.html#ggaf99eec425e4a077026c29fca5f2e7f47acf970cf0271de1cd2a74fa35073666dd">CY_SYSCLK_DPLL_HP_CLK50MHZ_1US_CNT_VAL</a> = 7U
<br />
 }<tr class="memdesc:gaf99eec425e4a077026c29fca5f2e7f47"><td class="mdescLeft">&#160;</td><td class="mdescRight">DPLL-HP wait mode selection enum.  <a href="group__group__sysclk__pll__structs.html#gaf99eec425e4a077026c29fca5f2e7f47">More...</a><br /></td></tr>
</td></tr>
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<h2 class="groupheader">Enumeration Type Documentation</h2>
<a id="gaf99eec425e4a077026c29fca5f2e7f47"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf99eec425e4a077026c29fca5f2e7f47">&#9670;&nbsp;</a></span>cy_en_wait_mode_select_t</h2>

<div class="memitem">
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          <td class="memname">enum <a class="el" href="group__group__sysclk__pll__structs.html#gaf99eec425e4a077026c29fca5f2e7f47">cy_en_wait_mode_select_t</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DPLL-HP wait mode selection enum. </p>
<p>See CONFIG2 register, bits MODE_SEL. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ggaf99eec425e4a077026c29fca5f2e7f47a030904943a55de752048728289437ae3"></a>CY_SYSCLK_DPLL_HP_CLK4MHZ_1US_CNT_VAL&#160;</td><td class="fielddoc"><p>clk_dig frequency = 4MHz </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaf99eec425e4a077026c29fca5f2e7f47ac907d199f7ebde8e2ebe0f0f71e6cea0"></a>CY_SYSCLK_DPLL_HP_CLK10MHZ_1US_CNT_VAL&#160;</td><td class="fielddoc"><p>clk_dig frequency = 10MHz </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaf99eec425e4a077026c29fca5f2e7f47a3581bc4d3e968bba9f91209a583b7261"></a>CY_SYSCLK_DPLL_HP_CLK15MHZ_1US_CNT_VAL&#160;</td><td class="fielddoc"><p>clk_dig frequency = 15MHz </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaf99eec425e4a077026c29fca5f2e7f47ae3a306e2ba52c1aed04d1fbd977c1eae"></a>CY_SYSCLK_DPLL_HP_CLK20MHZ_1US_CNT_VAL&#160;</td><td class="fielddoc"><p>clk_dig frequency = 20MHz </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaf99eec425e4a077026c29fca5f2e7f47ac3972a0491f06b1efa46cbe78178cb2e"></a>CY_SYSCLK_DPLL_HP_CLK30MHZ_1US_CNT_VAL&#160;</td><td class="fielddoc"><p>clk_dig frequency = 30MHz </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaf99eec425e4a077026c29fca5f2e7f47a7235d2e5aaa2b4db0c0e8c9ee7ebc818"></a>CY_SYSCLK_DPLL_HP_CLK40MHZ_1US_CNT_VAL&#160;</td><td class="fielddoc"><p>clk_dig frequency = 40MHz </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaf99eec425e4a077026c29fca5f2e7f47ac81cadd73490b1cb782c2a41ec422d9d"></a>CY_SYSCLK_DPLL_HP_CLK45MHZ_1US_CNT_VAL&#160;</td><td class="fielddoc"><p>clk_dig frequency = 45MHz </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaf99eec425e4a077026c29fca5f2e7f47acf970cf0271de1cd2a74fa35073666dd"></a>CY_SYSCLK_DPLL_HP_CLK50MHZ_1US_CNT_VAL&#160;</td><td class="fielddoc"><p>clk_dig frequency = 50MHz </p>
</td></tr>
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